Eecs:1100 Digital Logic Design Final Examination Eith Answers - Dr. Anthony D. Johnson, The University Of Toledo Page 8
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8The University of Toledo
f15fs_dild7.fm - 8
EECS:1100 Digital Logic Design
Dr. Anthony D. Johnson
Student
name
______________________________________
3.6 In the space reserved for Figure 3.3 prepare the logic circuit model of the designed implementation
of the State Machine whose ASM chart is shown in Figure 3.1(a).
2
Y
FF1
1
y
A
1
D
Q
y
Q
1
X
Y
FF2
y
2
2
D
Q
CLK
Q
.
Figure 3.3 Logic circuit model of the State Machine whose ASM chart is shown in Figure 3.1(a)
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