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Eecs:1100 Digital Logic Design Final Examination Eith Answers - Dr. Anthony D. Johnson, The University Of Toledo Page 5

The University of Toledo

f15fs_dild7.fm - 5

EECS:1100 Digital Logic Design

Dr. Anthony D. Johnson

Student

name

______________________________________

Hint #1 For full credit: all equations, all answers to questions, all circuit models and other

graphical representations are expected to be entered into the space designated for them;

all shown numerical results must be preceded by the

symbolic and numeric

expressions

whose evaluation produces the shown results.

Problem Solution

For full credit, explicit demonstration of understanding the following solution steps is expected.

2.1 Using for the input signals to the shift register the following designations:

- for the shift right operation: I

- for the shift left operation: I

- for parallel load operation: I

through I

design and enter in Figure 2.1(a) the necessary connections to make the completed circuit model

of Figure 2.1(a) implement the universal shift register specified by the function table shown in

Figure 2.1(b).

2.2 In the space reserved for Figure 2-1(c), write the signal designations from Figure 2.1(a) which

represent the serial outputs of the register for the shift left and shift right operations.

Eecs:1100 Digital Logic Design Final Examination Eith Answers - Dr. Anthony D. Johnson, The University Of Toledo Page 5